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FPGA Mezzanine Card (FMC) per VITA 57
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TI ADC12J4000 ADC
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Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
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Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
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Bypass Mode for full Nyquist output bandwidth
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Analog Devices AD9129 DAC
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DC-to-1.4 GHz in Baseband mode
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DC-to-1.0 GHz in 2x Interpolation mode
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1.4 to 4.2 GHz in Mix-Mode
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Supported by DAQ Series™ data acquisition software
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Excellent dynamic performance
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Front panel interface includes CLK In, Trig In, Analog In/Out, and GPIO
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Ultra Low-Noise wide-band PLL
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On-chip delay locked loops (DLLs) optimize timing between different clock domains.
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